WebApr 13, 2024 · An ITO/ZnTe/p-CdTe with the insertion of a CdS buffer layer between the ITO and i-ZnTe is the structure shown in Figure 17a, which exhibits strong rectifying diode characteristics. The PCE measured for the open circuit voltage (V oc), short circuit current density (J sc) and short circuit area was 0.77 V, 0.016 A/cm 2 and 19.6% WebSep 2, 2002 · As the CdTe layer was grown on CdS layer, the measured value of mobility is considered to have contributions from both the layers. For a comparison, the mobility of a single crystal CdTe is...
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WebAug 6, 2024 · In general, the density of inclusions in CdTe/CdZnTe can vary from 10 4 cm −3 to 10 6 cm −3 which can be controlled by adjusting temperature gradient at the melt-crystal interface, growth rate, melt stoichiometry, post-growth cooling, and application of forced convection (e.g., ACRT) [9, 56, 59, 60]. WebApr 6, 2024 · The optimum thickness, doping concentration, and defect density of the CIGS absorber were found at 1 µm, 10 18, and 10 14 cm −3, respectively, with a ZnSe buffer layer thickness of 0.05 µm and interfacial defect density of 10 10 cm −2 for the both ZnSe/CIGS and CIGS/V 2 O 5 interfaces. newbww gaming chair
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WebHence the ZnO/CdS bilayer window is adopted and demonstrated that the cell efficiency can be increased up to 17.66% with current density of 28.4 mA/cm2 and 73.7% fill factor. AB … WebApr 13, 2024 · An ITO/ZnTe/p-CdTe with the insertion of a CdS buffer layer between the ITO and i-ZnTe is the structure shown in Figure 17a, which exhibits strong rectifying diode characteristics. The PCE measured for the open circuit voltage (V oc), short circuit … WebN2 - The authors investigate the mechanism by which the carrier density of p-CdTe:P decreases due to heat treatment. By successive etching of a heat-treated sample, a … newbxbox one updates